1. Field of the Invention
The invention relates to microcontrollers and computer systems, and more particularly to microcontrollers which need to select a clock from a variety of possible clock sources.
2. Description of the Related Art
Specialized microcontrollers with integrated communication features are becoming particularly attractive for communications applications. A microcontroller, or an embedded controller, is uniquely suited to combining functionality onto one monolithic semiconductor substrate (i.e. chip). By embedding various communication features within a single chip, a communications microcontroller may support a wide range of communication applications.
Microcontrollers have been used for many years in many applications. A number of these applications involve communications over electronic networks, such as telephone lines, computer networks, and local and wide area networks, in both digital and analog formats. In communications applications, a microcontroller generally has a number of integrated communications peripherals in addition to the execution unit. These can be low and high speed serial ports, as well as more sophisticated communications peripherals, such as a universal serial bus (USB) interface, and high level data link control (HDLC) channels.
For high-speed communications that use frames of data, HDLC channels are especially well suited. An HDLC channel transmits and receives frames based on the HDLC format. This format uses flags to determine the start and stop of a frame, and uses “bit stuffing” to maintain data transparency. An HDLC channel, however, is a general purpose device, and can be employed to implement a number of communications protocols, such as the serial circuit interface (GCI) protocol (similar to an IOM-2 protocol) sometimes used for ISDN (integrated services digital network) communications (similar to the IOM-2 protocol), a pulse coded modulation (PCM) highway protocol, as well as raw data communications equipment (DCE) formats. These formats are synchronous communication protocols that may or may not include a separate clock.
But communications employing the HDLC format can be further implemented within time slots of a lower level time division multiplexed framing protocol, such as a T1 or E1 protocol. This protocol employs 24 or 32 time slots of 8 bits each, and each time slot could be used to carry different communications data, even in different formats. In such protocols, the time slots are determined based on a frame sync signal, which can be embedded in the data stream, be embedded in a clock stream, or even a separate signal, depending on the communications protocol. Each such time slot, for example, could be implemented to carry a separate HDLC channel of data.
Further, a time slot assigner (TSA) can be coupled in a microcontroller to an HDLC channel for slot-level placement of the HDLC data on the external communication path. Such a TSA determines the start of a programmed time slot relative to the frame sync. This could be to provide the HDLC data within a particular time slot, or to further implement some sort of protocol that employs its own time slots, such as the protocol used for ISDN. In the GCI protocol, a frame is subdivided into two 8-bit B channels and a 2-bit D channel, which form two separate 8-bit and one 2-bit “slot” within a communications frame on the GCI bus.
More generally, a time slot assigner (TSA) typically supports the isolation of 8-bit slots from 0 to 155 on a standard 8-kilohertz time division multiplexed (TDM) frame. This supports a variety of TDM buses, including GCI, E1, T1, PCM highway, and others. Of course, other length frames, other speeds, and other numbers of slots can be supported as well.
Support for multiple communications protocols has typically implied multiple clock sources are present. For a processor-based device, when a clock source from a number of clock sources must be selected for a clock line, clock glitches, unwanted signal transitions or edges on the clock line, often very short, have commonly occurred on the clock line during switching of a clock source to the clock line. The timing of processor-based devices thus has been susceptible to such clock glitches. Clock behavior has been particularly critical for processor-based devices that support multiple data communication protocols such as those described above.